Japanese Patent Application No. 2000-397122, filed on Dec. 27, 2000, is hereby incorporated by reference in its entirety.
The present invention relates to a ferroelectric memory device and a method of operating memory cells including ferroelectric capacitors. More particularly, the present invention relates to a simple matrix type ferroelectric memory device and a method of operating memory cells including ferroelectric capacitors.
A simple matrix type ferroelectric memory device using only ferroelectric capacitors instead of cell transistors has a very simple structure and enables a higher degree of integration. Therefore, development of such a memory device has been expected.
Japanese Patent Application Laid-open No. 9-116107 discloses technology relating to a simple matrix type ferroelectric memory device and an operation method therefor.
A method of writing and reading data disclosed in Japanese Patent Application Laid-open No. 9-116107 is described below. FIG. 7 is a view showing a memory cell array of a ferroelectric memory device.
The method of writing data is described below. FIG. 8 is a timing chart in the case of writing data xe2x80x9c1xe2x80x9d into a ferroelectric capacitor Cm,N and writing data xe2x80x9c0xe2x80x9d into Cm,N+1. In the technology according to Japanese Patent Application Laid-open No. 9-116107, the data xe2x80x9c1xe2x80x9d is written into a memory cell by applying a voltage in a direction so that the potential of a selected sub-bit line is higher than the potential of a selected word line. The data xe2x80x9c0xe2x80x9d is written into the memory cell by applying a voltage in a direction so that the potential of the selected sub-bit line is lower than the potential of the selected word line.
Main bit lines MBLN and MBLN+1 are set to a ground voltage (0 V) at time t1. At the same time, a selection gate line SL is set to 5 V from 0 V, a selected word line WLm is set to a power supply voltage VCC (3.3 V), and all non-selected word lines WL1-WLM are set to the ground voltage (0 V). This causes the contents of the ferroelectric capacitors Cm,N and Cm,N+1 to be erased (data xe2x80x9c0xe2x80x9d is written).
At time t2, the selection gate line SL and the selected word line WLm are set to the ground voltage (0 V), the main bit line MBLN is set to the power supply voltage VCC (3.3 V), and the main bit line MBLN+1 is set to (⅓) VCC (1.1 V).
At time t3, the selection gate line SL is set to 5 V, the selected word line WLm is set to the ground voltage (0 V), and the non-selected word lines WL1-WLM are set to (⅔) VCC (2.2 V). This causes the data xe2x80x9c1xe2x80x9d to be written into the ferroelectric capacitor Cm,N.
At time t4, the main bit lines MBLN and MBLN+1 are set to (⅓) VCC (1.1 V), and the selection gate line SL and the word lines WL1-WLM are set to the ground voltage (0 V), whereby the write operation is completed.
The method of reading data is described below. FIG. 9 is a timing chart in the case of reading the data xe2x80x9c1xe2x80x9d stored in the memory cell Cm,N and reading the data xe2x80x9c0xe2x80x9d stored in the memory cell Cm,N+1, and rewriting the data xe2x80x9c1xe2x80x9d into the memory cell Cm,N and rewriting the data xe2x80x9c0xe2x80x9d into Cm,N+1.
At time t1, a precharge signal xcfx86PC is set to the power supply voltage VCC (3.3 V), and a column select signal xcfx86 is set to 5 V. This causes the main bit lines MBLN and MBLN+1 to be precharged to a precharge voltage VPC (0 V) before time t2. The main bit lines MBLN and MBLN+1 are respectively connected to nodes VN and VN+1 of sense amplifiers.
A time t2, the precharge signal xcfx86PC is set to 0 V, thereby causing the main bit lines MBLN and MBLN+1 to be in a floating state. The selection gate line SL is set to 5 V from 0 V, and the selected word line WLm is set to the power supply voltage VCC (3.3 V) from 0 V. This causes the ferroelectric capacitors Cm,N and Cm,N+1 to be in a polarization state in which the data xe2x80x9c0xe2x80x9d is written.
At time t3, the selection gate line SL and the selected word line WLm are set to 0 V. At time t4, a sense enable signal xcfx86SE is set to the power supply voltage VCC (3.3 V). This causes sense amplifiers SAN and SAN+1 to be activated. As a result, the data xe2x80x9c1xe2x80x9d is latched by the sense amplifier SAN before time t5, whereby the potential of the main bit line MBLN is set to the power supply voltage VCC (3.3 V). The data xe2x80x9c0xe2x80x9d is latched by the sense amplifier SAN+1, whereby the potential of the main bit line MBLN+1 is set to the ground voltage (0 V) The read operation is performed in this manner.
Since steps after time t5 are rewriting steps, description thereof is omitted.
The present invention may provide a ferroelectric memory device and a method of operating memory cells including ferroelectric capacitors capable of preventing malfunctions of the ferroelectric memory device.
1. Ferroelectric memory device
(A) A first ferroelectric memory device of the present invention comprises:
first signal electrodes, a ferroelectric layer, and second signal electrodes,
wherein the second signal electrodes are formed along a direction which intersects with the first signal electrodes,
wherein memory cells each of which comprises a ferroelectric capacitor including at least one of the first signal electrodes, one of the second signal electrodes, and the ferroelectric layer, are formed in regions in which the first signal electrodes intersect the second signal electrodes,
wherein information is written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in the selected memory cell, and
wherein an absolute value of the write voltage is less than an absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitor is saturated.
In this aspect of the present invention, the absolute value of the write voltage is less than the absolute value of the saturation voltage. This enables the difference between switching polarization and non-switching polarization to be increased in comparison with the case of setting the write voltage the same as the saturation voltage. Therefore, the difference in bit line potential between reading of first data and reading of second data can be increased, whereby malfunctions can be decreased.
The ferroelectric memory device of this aspect of the present invention may have any of the following features.
(a) Information may be read from a selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in the selected memory cell, and
an absolute value of the read voltage may be less than an absolute value of a saturation voltage.
In this case, the absolute value of the write voltage may be the same as the absolute value of the read voltage.
In addition, while information is read from a selected memory cell, part of information may be written into the selected memory cell.
(b) A first voltage which prevents polarization inversion of a non-selected memory cell may be applied between one of the first signal electrodes and one of the second signal electrodes in the non-selected memory cell when information is written into the selected memory cell, and
the maximum absolute value of the first voltage may be half of the absolute value of the write voltage.
(c) A second voltage which prevents polarization inversion of a non-selected memory cell may be applied between one of the first signal electrodes and one of the second signal electrodes in the non-selected memory cell when information is read from the selected memory cell, and
the maximum absolute value of the second voltage may be half of the absolute value of the read voltage.
(B) A second ferroelectric memory device of the present invention comprises:
first signal electrodes, a ferroelectric layer, and second signal electrodes,
wherein the second signal electrodes are formed along a direction which intersects the first signal electrodes,
wherein memory cells each of which comprises a ferroelectric capacitor including at least one of the first signal electrodes, one of the second signal electrodes, and the ferroelectric layer, are formed in regions in which the first signal electrodes intersect the second signal electrodes,
wherein information is written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in the selected memory cell,
wherein information is read from the selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in the selected memory cell, and
wherein, provided that the write voltage is xc2x1Vs and the read voltage is one of +Vs and xe2x88x92Vs, |Vs| is less than an absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitor is saturated.
In this aspect of the present invention, |Vs| is less than the absolute value of the saturation voltage at which remanent polarization of the ferroelectric capacitor is saturated. Therefore, the write voltage is less than the saturation voltage. As a result, effects the same as those of the first ferroelectric memory device of the present invention can be achieved.
The second ferroelectric memory device of the present invention may have any of the following features.
(a) A first voltage which prevents polarization inversion of a non-selected memory cell may be applied between one of the first signal electrodes and one of the second signal electrodes in the non-selected memory cell when information is written into the selected memory cell, and
wherein the maximum absolute value of the first voltage may be (xc2xd) |Vs|.
(b) A second voltage which prevents polarization inversion of a non-selected memory cell may be applied between one of the first signal electrodes and one of the second signal electrodes in the non-selected memory cell when information is read from the selected memory cell, and
the maximum absolute value of the second voltage may be (xc2xd) |Vs|.
In the first and second ferroelectric memory devices of the present invention, the ferroelectric layer may be formed of a perovskite-type oxide ferroelectric.
The ratio of the absolute value of the write voltage to the thickness of the ferroelectric layer is preferably 17 V/xcexcm or less, and still more preferably 15 V/xcexcm or less.
The ferroelectric layer is formed of a material having a relative dielectric constant of preferably 400 or less, and still more preferably 300 or less in a state in which the bias voltage is not applied.
2. Method of Operating Memory Cell
(A) In a first method of operating memory cells including ferroelectric capacitors of the present invention,
each of the memory cells comprises a first signal electrode, a ferroelectric layer, and a second signal electrode,
the second signal electrode is formed along a direction which intersects with the first signal electrode,
each of the memory cells comprises at least the first signal electrode, the second signal electrode, and the ferroelectric layer in a region in which the first signal electrode intersects the second signal electrode, the method comprises:
a step of writing information into a selected memory cell by applying a write voltage between the first signal electrode and the second signal electrode in the selected memory cell,
wherein an absolute value of the write voltage is less than an absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitors is saturated.
According to the operation method of this aspect of the present invention, the absolute value of the write voltage is set less than the absolute value of the saturation voltage when writing information into the memory cell. Therefore, the difference between switching polarization and non-switching polarization can be increased in comparison with the case of setting the write voltage the same as the saturation voltage. Therefore, the difference in bit line potential between reading of the first data and reading of the second data can be increased, whereby malfunctions can be further decreased.
The first method of operating a memory cell of the present invention may have any of the following features.
(a) The method may further comprises:
a step of reading information from the selected memory cell by applying a read voltage between the first signal electrode and the second signal electrode in the selected memory cell,
wherein an absolute value of the read voltage may be less than an absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitors is saturated.
In this case, the absolute value of the write voltage may be the same as the absolute value of the read voltage.
In addition, while information is read from a selected memory cell, part of information may be written into the selected memory cell.
(b) A first voltage which prevents polarization inversion of a non-selected memory cell may be applied between the first signal electrode and the second signal electrode in the non-selected memory cell when information is written into the selected memory cell, and
the maximum absolute value of the first voltage may be half of the absolute value of the write voltage.
(c) A second voltage which prevents polarization inversion of a non-selected memory cell may be applied between the first signal electrode and the second signal electrode in the non-selected memory cell when information is read from the selected memory cell, and
the maximum absolute value of the second voltage may be half of the absolute value of the read voltage.
(B) In a second method of operating memory cells including ferroelectric capacitors of the present invention,
each of the memory cells comprises a first signal electrode, a ferroelectric layer, and a second signal electrode,
the second signal electrode is formed along a direction which intersects with the first signal electrode,
each of the memory cells comprises at least the first signal electrode, the second signal electrode, and the ferroelectric layer in a region in which the first signal electrode intersects the second signal electrode, the method comprises:
a step of writing information into a the selected memory cell by applying a write voltage between the first signal electrode and the second signal electrode in the selected memory cell, and
a step of reading information from the selected memory cell by applying a read voltage between the first signal electrode and the second signal electrode in the selected memory cell,
wherein, provided that the write voltage is xc2x1Vs and the read voltage is one of +Vs and xe2x88x92Vs, |Vs| is less than an absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitors is saturated.
In the second method of operating memory cells of the present invention, the absolute value |Vs| of the write voltage is less than the absolute value of the saturation voltage. Therefore, effects the same as those of the first method of operating memory cells of the present invention can be achieved.
The second method of operating memory cells of the present invention may have any of the following features.
(a) A first voltage which prevents polarization inversion of a non-selected memory cell may be applied between the first signal electrode and the second signal electrode in the non-selected memory cell when information is written into the selected memory cell, and
the maximum absolute value of the first voltage may be (xc2xd) |Vs|.
(b) A second voltage which prevents polarization inversion of a non-selected memory cell may be applied between the first signal electrode and the second signal electrode in the non-selected memory cell when information is read from the selected memory cell, and
the maximum absolute value of the second voltage may be (xc2xd) |Vs|.
In the first and second method of operating a memory cell of the present invention, the ferroelectric layer may be formed of a perovskite-type oxide ferroelectric.